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| HIP4086 Data Sheet May 1999 File Number 4220.4 80V, 0.5A Three Phase Driver The HIP4086 is a Three Phase Bridge N-Channel MOSFET driver IC. The HIP4086 is specifically targeted for PWM motor control. It makes bridge based designs simple and flexible. Like the HIP4081, the HIP4086 has a flexible input protocol for driving every possible switch combination. Unlike the HIP4081, the user can override the shoot-through protection for switched reluctance applications. The HIP4086 has reduced drive current compared to the HIP4081 (0.5A vs 2.5A) and a much wider range of programmable dead times (0.25s to 4.5s) - like the HIP4082. The HIP4086 is suitable for applications requiring DC to 100kHz. Unlike the previous family members, the HIP4086 has a programmable undervoltage set point. Also refer to the HIP4083, three phase upper only MOSFET driver, for a lower current solution optimized for smaller motors. Features * Independently Drives 6 N-Channel MOSFETs in Three Phase Bridge Configuration * Bootstrap Supply Max Voltage to 95VDC * Bias Supply Operation from 7V to 15V * 1.25A Peak Turn-Off Current * User-Programmable Dead Time (0.25s to 4.5s) * Charge-Pump and Bootstrap Maintain Upper Bias Supplies * Programmable Bootstrap Refresh Time * Drives 1000pF Load with Typical Rise Time of 20ns and Fall Time of 10ns * DIS (Disable) Overrides Input Control * Input Logic Thresholds Compatible with 5V to 15V Logic Levels * Dead Time Disable Capability Ordering Information PART NUMBER HIP4086AB HIP4086AP TEMP. RANGE (oC) -40 to 125 -40 to 125 PACKAGE 24 Ld SOIC 24 Ld PDIP PKG. NO. M24.3 E24.3 * Programmable Undervoltage Set Point Applications * Brushless Motors * AC Motor Drives Pinout HIP4086 (PDIP, SOIC) TOP VIEW BHB 1 BHI 2 BLI ALI 3 4 24 BHO 23 BHS 22 BLO 21 ALO 20 VDD 19 CLO 18 AHS 17 AHO 16 AHB 15 CHS 14 CHO 13 CHB * Switched Reluctance Motor Drives * Battery Powered Vehicles Application Block Diagram 80V 12V AHI 5 VSS 6 RDEL 7 UVLO 8 RFSH 9 DIS 10 CLI 11 CHI 12 HIP4086 GND GND 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 HIP4086 Functional Block Diagram (1/3 of HIP4086 ) CHARGE PUMP 16 AHB AHI 5 DRIVER TURN-ON DELAY 10ns DELAY UV LEVEL SHIFTER UV DEAD TIME DISABLE 20 VDD DRIVER TURN-ON DELAY ALI RDEL 4 7 DEAD TIME CURRENT MIRRORS + 100mV + VSS 2s DELAY 21 ALO 6 DEAD TIME DISABLE VSS 17 AHO 18 AHS DIS 10 VDD 20 UVLO 8 UNDERVOLTAGE DETECTOR RFSH 9 RFSH PULSE TRUTH TABLE INPUT ALI, BLI, CLI X X 1 0 0 1 AHI, BHI, CHI X X X 0 1 0 UV X 1 0 0 0 0 DIS 1 X 0 0 0 0 RDEL X X >100mV X X <100mV 0 0 1 0 0 1 OUTPUT ALO, BLO, CLO AHO, BHO, CHO 0 0 0 1 0 1 NOTE: X signifies that input can be either a "1" or "0". Typical Application (PWM Mode Switching) +12V 80V +12V 1 BHB 2 BHI RDEL PWM INPUTS 3 BLI 4 ALI 5 AHI 6 VSS 7 RDEL 8 UVLO 9 RFSH RUV (OPTIONAL) CRFSH (OPTIONAL) FROM OPTIONAL OVERCURRENT LATCH 10 DIS 11 CLI 12 CHI BHO 24 BHS 23 BLO 22 ALO 21 VDD 20 CLO 19 AHS 18 AHO 17 AHB 16 CHS 15 CHO 14 CHB 13 GND RDIS 3-PHASE LOAD 2 HIP4086 Pin Descriptions PIN NUMBER 16 1 13 SYMBOL AHB BHB CHB (xHB) AHI BHI CHI (xHI) DESCRIPTION High-Side Bootstrap supplies. One external bootstrap diode and one capacitor are required for each. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to each xHB pin. 5 2 12 High-Side Logic Level Inputs. Logic at these three pins controls the three high side output drivers, AHO (Pin 17), BHO (Pin 24) and CHO (Pin 14). When xHI is low, xHO is high. When xHI is high, xHO is low. Unless the dead time is disabled by connecting RDEL (Pin 7) to ground, the low side input of each phase will override the corresponding high side input on that phase - see Truth Table on previous page. If RDEL is tied to ground, dead time is disabled and the outputs follow the inputs. Care must be taken to avoid shoot-through in this application. DIS (Pin 10) also overrides the high side inputs. xHI can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100A pull-up to VDD will hold each xHI high if the pins are not driven. Low-Side Logic Level Inputs. Logic at these three pins controls the three low side output drivers ALO (Pin 21), BLO (Pin 22) and CLO (Pin 19). If the upper inputs are grounded then the lower inputs control both xLO and xHO drivers, with the dead time set by the resistor at RDEL (Pin 7). DIS (Pin 10) high level input overrides xLI, forcing all outputs low. xLI can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100A pull-up to VDD will hold xLI high if these pins are not driven. Ground. Connect the sources of the Low-Side power MOSFETs to this pin. Dead Time Setting. Connect a resistor from this pin to VDD to set timing current that defines the dead time between drivers - see Figure 15. All drivers turn-off with no adjustable delay, so the RDEL resistor guarantees no shoot-through by delaying the turn-on of all drivers. When RDEL is tied to VSS, both upper and lowers can be commanded on simultaneously. While not necessary in most applications, a decoupling capacitor of 0.1F or smaller may be connected between RDEL and VSS. Undervoltage Setting. A resistor can be connected between this pin and VSS to program the undervoltage set point, see Figure 16. With this pin not connected, the undervoltage disable is typically 6.6V. When this pin is tied to VDD, the undervoltage disable is typically 6.2V. Refresh Pulse Setting. An external capacitor can be connected from this pin to V SS to increase the length of the start up refresh pulse - see Figure 14. If this pin is not connected, the refresh pulse is typically 1.5s. Disable Input. Logic level input that when taken high sets all six outputs low. DIS high overrides all other inputs. With DIS low, the outputs are controlled by the other inputs. DIS can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100A pull-up to VDD will hold DIS high if this pin is not driven. High-Side Outputs. Connect to the gates of the High-Side power MOSFETs in each phase. 4 3 11 ALI BLI CLI (xLI) 6 7 VSS RDEL 8 UVLO 9 RFSH 10 DIS 17 24 14 AHO BHO CHO (xHO) AHS BHS CHS (xHS) VDD ALO BLO CLO (xLO) 15 23 15 High-Side Source Connection. Connect the sources of the High-Side power MOSFETs to these pins. The negative side of the bootstrap capacitors should also be connected to these pins. 20 21 22 19 Positive Supply. Decouple this pin to VSS (Pin 6). Low-Side Outputs. Connect the gates of the Low-Side power MOSFETs to these pins. NOTE: x = A, B and C. 3 HIP4086 Absolute Maximum Ratings Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on xHS . . . . . . . . . -6V (Transient) to 85V (-40oC to 150oC) Voltage on xHB . . . . . . . . . . . . . . . . . . . . VxHS -0.3V to VxHS +VDD Voltage on xLO . . . . . . . . . . . . . . . . . . . . . VSS -0.3V to VDD +0.3V Voltage on xHO . . . . . . . . . . . . . . . . . . . . VxHS -0.3V to VxHB +0.3V Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns Thermal Information Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V to +15V Voltage on xHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VxHS + VDD Voltage on xHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 80V Ambient Temperature Range . . . . . . . . . . . . . . . . . . -40oC to 125oC Junction Temperature Range . . . . . . . . . . . . . . . . . . -40oC to 150oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air. 2. All voltages are relative to VSS unless otherwise specified. 3. x = A, B and C. For example, xHS refers to AHS, BHS and CHS. Electrical Specifications VDD = VxHB = 12V, VSS = VxHS = 0V, RDEL = 20K, RUV = , Gate Capacitance (CGATE) = 1000pF TJ = 25oC TJ = -40oC TO 150oC MAX MIN MAX UNITS PARAMETER TEST CONDITIONS MIN TYP SUPPLY CURRENTS AND UNDER VOLTAGE PROTECTION VDD Quiescent Current VDD Operating Current xHB On Quiescent Current xHB Off Quiescent Current xHB Operating Current Qpump Output Voltage Qpump Output Current xHB, xHS Leakage Current VDD Rising Undervoltage Threshold VDD Falling Undervoltage Threshold Minimum Undervoltage Threshold xHI = 5V, xLI = 5V f = 20kHz, 50% Duty Cycle xHI = 0V xHI = VDD f = 20kHz, 50% Duty Cycle No Load VxHS = 12V, VxHB = 22V VxHS = 80V, VxHB = 93V RUV open RUV open RUV = VDD 2.7 6.3 0.6 0.7 11.5 50 7 6.2 5.75 5 3.4 8.25 40 0.8 0.9 12.5 100 24 7.1 6.6 6.2 4.2 10.5 80 1.3 1.3 14 130 45 8.0 7.5 6.8 2.1 5 0.5 10.5 6.1 5.6 4.9 4.3 11 100 1.4 2.0 14.5 140 50 8.1 7.6 6.9 mA mA A mA mA V A A V V V INPUT PINS: ALI, BLI, CLI, AHI, BHI, CHI, AND DIS Low Level Input Voltage High Level Input Voltage Input Voltage Hysteresis Low Level Input Current High Level Input Current VIN = 0V VIN = 5V 2.5 60 -1 35 100 1.0 135 +1 2.7 55 -10 0.8 140 +10 V V mV A A GATE DRIVER OUTPUT PINS: ALO, BLO, CLO, AHO, BHO, AND CHO Low Level Output Voltage (VOUT - VSS) Peak Turn-On Current Peak Turn-Off Current ISINKING = 30mA VOUT = 0V VOUT = 12V 0.3 0.7 100 0.5 1.1 0.7 1.5 0.5 200 1.0 1.7 mV A A 4 HIP4086 Switching Specifications VDD = VxHB = 12V, VSS = VxHS = 0V, CGATE = 1000pF, RDEL = 10k TJ = 25oC PARAMETER TURN-ON DELAY AND PROPAGATION DELAY Dead Time RDEL = 100K RDEL = 10K Dead Time Channel Matching Lower Turn-Off Propagation Delay (xLI-xLO) Upper Turn-Off Propagation Delay (xHI-xHO) Lower Turn-On Propagation Delay (xLI-xLO) Upper Turn-On Propagation Delay (xHI-xHO) Rise Time Fall Time Disable Turn-Off Propagation Delay (DIS - Lower Outputs) Disable Turn-Off Propagation Delay (DIS - Upper Outputs) Disable to Lower Turn-On Propagation Delay (DIS - xLO) Disable to Upper Enable (DIS - xHO) Refresh Pulse Width (xLO) RDEL = 10K, CRFSH Open CRFSH Open RDEL = 10K No Load No Load No Load No Load CGATE = 1000pF CGATE = 1000pF 3.8 0.38 4.5 0.5 7 30 75 45 65 20 10 55 80 55 2.0 1.5 6 0.65 15 45 90 75 90 40 20 80 90 80 3 0.3 7 0.7 20 65 100 90 100 50 25 90 100 100 s s % ns ns ns ns ns ns ns ns ns s s TEST CONDITIONS MIN TYP MAX TJ = -40oC TO 150oC MIN MAX UNITS 5 HIP4086 Timing Diagrams LOWER TURN-OFF LOWER TURN-ON XLI XHI XLO XHO DEAD TIME XLO (RDEL = VSS) DEAD TIME XHO (RDEL = VSS) UPPER TURN-ON UPPER TURN-OFF FIGURE 1. DISABLE TO LOWER TURN-ON PROP DELAY REFRESH PULSE WIDTH DISABLE TURN-OFF PROP DELAY (UPPERS) DIS OR UV XHI, XLI XLO XHO DISABLE TO UPPER ENABLE FIGURE 2. DISABLE FUNCTION NOTES: 4. X means any "A", "B", or "C" phase. 5. With RDEL resistor tied to VDD, lowers and uppers cannot be turned on at the same time. Low side logic overrides high side logic unless RDEL < 100mV. 6 HIP4086 Typical Performance Curves 6 VDD = 16V VDD SUPPLY CURRENT (mA) 5 ALL GATE CONTROL INPUTS = 5V VDD SUPPLY CURRENT (mA) 200kHz 25 100kHz 20 50kHz 30 CGATE = 1000pF VDD = 15V VDD = 12V 4 VDD = 10V 3 VDD = 8V VDD = 7V 2 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 140 160 15 20kHz 10kHz 10 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 140 160 FIGURE 3. VDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE FIGURE 4. VDD SUPPLY CURRENT vs SWITCHING FREQUENCY 4000 FLOATING BIAS CURRENT (A) TJ = 25oC BIAS CURRENT (mA) 3000 CGATE = 1000pF 2000 1.8 VDD = 15V 1.6 1.4 1.2 1.0 0.8 0.6 -60 VDD = 10V VDD = 8V VDD = 7V 1000 CGATE = NO LOAD 0 VDD = 12V 0 20 40 60 80 100 120 140 160 SWITCHING FREQUENCY (kHz) 180 200 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 140 160 FIGURE 5. FLOATING IXHB BIAS CURRENT FIGURE 6. OFF-STATE IXHB BIAS CURRENT 200 CHARGE PUMP OUTPUT VOLTAGE (V) VxHB - VxHS = 10V OUTPUT CURRENT (A) 150 14 13 12 11 10 9 8 7 6 -60 -40 -20 0 20 40 60 80 100 120 140 160 VDD = 8V VDD = 12V VDD = 10V VDD = 15V 100 50 VDD = 7V 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 JUNCTION TEMPERATURE (oC) JUNCTION TEMPERATURE (oC) FIGURE 7. CHARGE PUMP OUTPUT CURRENT FIGURE 8. CHARGE PUMP OUTPUT VOLTAGE 7 HIP4086 Typical Performance Curves 1 AVERAGE TURN-OFF CURRENT (A) AVERAGE TURN-ON CURRENT (A) CGATE = 1000pF 0.8 VDD = 15V 0.6 VDD = 12V VDD = 10V 0.4 V DD = 8V VDD = 7V (Continued) 2 VDD = 15V 1.6 VDD = 12V 1.2 VDD = 10V VDD = 8V VDD = 7V 0.4 CGATE = 1000pF 0.8 0.2 0 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 140 160 0 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 140 160 FIGURE 9. AVERAGE TURN-ON CURRENT (0 TO 5V) FIGURE 10. AVERAGE TURN-OFF CURRENT (VDD TO 4V) 40 VDD = XHB-XHS = 12V, CGATE = 1000pF RISE AND FALL TIMES (ns) PROPAGATION DELAY (ns) 30 RISE 20 FALL 10 100 80 xHI to xHO 60 40 xLI to xLO 0 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 140 160 20 -60 -40 -20 0 20 40 60 80 100 120 140 160 JUNCTION TEMPERATURE (oC) FIGURE 11. RISE AND FALL TIMES (10-90%) FIGURE 12. PROPAGATION DELAY 100 UPPER DISABLE TURN-OFF PROPAGATION DELAY (ns) REFRESH TIME (s) 80 TJ = 25oC 60 LOWER DISABLE TURN-OFF LOWER ENABLE TURN-ON 40 20 10 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 140 160 0 0 50 100 150 200 250 300 CRFSH (pF) 350 400 450 500 FIGURE 13. DISABLE PIN PROPAGATION DELAY FIGURE 14. REFRESH TIME 8 HIP4086 Typical Performance Curves 6 UNDERVOLTAGE SHUTDOWN/ ENABLE VOLTAGE RDEL = 100k (Continued) 11 10.5 10 9.5 9 8.5 8 7.5 7 6.5 TRIP/ENABLE (0K, UVLO TO VDD) ENABLE (UVLO OPEN) TRIP (UVLO OPEN) TRIP (50K, UVLO TO GND) ENABLE (50K, UVLO TO GND) DEAD TIME (s) 4 2 RDEL = 10k 0 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 140 160 6 -60 -40 -20 0 20 40 60 80 100 120 140 160 JUNCTION TEMPERATURE (oC) FIGURE 15. DEAD TIME FIGURE 16. UNDERVOLTAGE THRESHOLD 25 LEAKAGE CURRENT (A) VxHS = 80V 20 15 10 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 140 160 FIGURE 17. IxHS LEAKAGE CURRENT All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: 1-800-442-7747 (407) 727-9207 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 9 |
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